1. Field of the Invention
The present invention relates to a display device and a fabricating method thereof, and more particularly to a method of patterning a transparent conductive film wherein the transparent conductive film can be selectively etched without using any masks. Also, the present invention is directed to a method of fabricating a display device that is capable of reducing the number of mask processes using said method of patterning the transparent conductive film.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls light transmittance of a liquid crystal using an electric field to thereby display a picture. To this end, the LCD includes a liquid crystal panel having liquid crystal cells arranged in a matrix, and a driving circuit for driving the liquid crystal panel.
The liquid crystal display panel includes a thin film transistor substrate and a color filter substrate opposed to each other, a spacer positioned between two substrates so as to keep a constant cell gap, and a liquid crystal with which the cell gap is filled.
The thin film transistor substrate consists of gate lines and data lines, thin film transistors formed as a switching device for each intersection between the gate lines and the data lines, pixel electrodes formed for each liquid crystal cell and connected to the thin film transistor, and alignment films coated thereon. The gate lines and the data lines receive signals from the driving circuits via each pad portion. The thin film transistor applies a pixel voltage signal fed to the data line in response to a scanning signal fed to the scanning signal.
The color filter substrate consists of color filters formed for each liquid crystal cell, a black matrix for dividing color filters and reflecting an external light, a common electrode for commonly applying a reference voltage to the liquid crystal cells, and an alignment film coated thereon.
The liquid crystal display panel is completed by preparing the thin film array substrate and the color filter substrate individually to join them and then injecting a liquid crystal and sealing it.
In such a liquid crystal display panel, since the thin film transistor substrate involves a semiconductor process and requires a plurality of mask processes, the manufacturing process is complicate to be a major rise factor in the manufacturing cost of the liquid crystal display panel. In order to solve this, the thin film transistor substrate has been developed toward a reduction in the number of mask processes. This is because one mask process includes a lot of processes such as deposition, cleaning, photolithography, etching, photo-resist stripping and inspection processes, etc. Recently, there has been highlighted a four-mask process in which one mask process is reduced from the existent five-mask process that was a standard mask process.
FIG. 1 is a plan view illustrating a thin film transistor substrate adopting a four-mask process, and FIG. 2 is a section view of the thin film transistor substrate taken along the I-I′ line in FIG. 1.
Referring to FIG. 1 and FIG. 2, the thin film transistor substrate includes a gate line 2 and a data line 4 provided on a lower substrate 42 in such a manner to intersect each other with having a gate insulating film 44 therebetween, a thin film transistor 6 provided at each intersection, and a pixel electrode 18 provided at a cell area having a crossing structure. Further, the thin film transistor substrate includes a storage capacitor 20 provided at an overlapped portion between the pixel electrode 18 and the pre-stage gate line 2, a gate pad portion 26 connected to the gate line 2, and a data pad portion 34 connected to the data line 4.
The thin film transistor 6 allows a pixel signal applied to the data line 4 to be charged into the pixel electrode 18 and be kept in response to a scanning signal applied to the gate line 2. To this end, the thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, a drain electrode 12 connected to the pixel electrode 16, and an active layer 14 overlapping with the gate electrode 8 and defining a channel between the source electrode 10 and the drain electrode 12.
The active layer 14 overlapping with the source electrode 10 and the drain electrode 12 and including a channel portion between the source electrode 10 and the drain electrode 12 also overlaps with the data pad lower electrode 36, the storage electrode 22 and the data line 4. On the active layer 14, an ohmic contact layer for making an ohmic contact with the data pad lower electrode 36, the storage electrode 22, the data line 4, the source electrode 10 and the drain electrode 12 is further provided.
The pixel electrode 18 is connected, via a first contact hole 16 passing through a protective film 50, to the drain electrode 12 of the thin film transistor 6. The pixel electrode 18 generates a potential difference with respect to a common electrode provided at an upper substrate (not shown) by the charged pixel signal. This potential difference rotates a liquid crystal positioned between the thin film transistor substrate and the upper substrate owing to a dielectric anisotropy and transmits a light inputted, via the pixel electrode 18, from a light source (not shown) toward the upper substrate.
The storage capacitor 20 consists of a pre-stage gate line 2, a storage electrode 22 overlapping with the gate line with having the gate insulating film 44, the active layer 14 and the ohmic contact layer 48 therebetween, and a pixel electrode 18 overlapping with the storage electrode 22 with having the protective film 50 therebetween and connected via a second contact hole 24 provided in the protective film 50. The storage capacitor 20 allows a pixel signal charged in the pixel electrode 18 to be maintained stably until the next pixel signal is charged.
The gate line 2 is connected, via the gate pad portion 26, to a gate driver (not shown). The gate pad portion 26 consists of a gate pad lower electrode 28 extended from the gate line 2, and a gate pad upper electrode 32 connected, via a third contact hole 30 passing through the gate insulating film 44 and the protective film 50, to the gate pad lower electrode 28.
The data line 4 is connected, via the data pad portion 34, to the data driver (not shown). The data pad portion 34 consists of a data pad lower electrode 36 extended from the data line 4, and a data pad upper electrode 40 connected, via a fourth contact hole 38 passing through the protective film 50, to the data pad lower electrode 36.
Hereinafter, a method of fabricating the thin film transistor substrate having the above-mentioned structure adopting the four-round mask process will be described in detail with reference to FIG. 3A to FIG. 3D.
Referring to FIG. 3A, gate metal patterns including the gate line 2, the gate electrode 8 and the gate pad lower electrode 28 are provided on the lower substrate 42 using the first mask process.
More specifically, a gate metal layer is formed on the upper substrate 42 by a deposition technique such as a sputtering. Then, the gate metal layer is patterned by the photolithography and the etching process employing a first mask to thereby form the gate metal patterns including the gate line 2, the gate electrode 8 and the gate pad lower electrode 28. The gate metal has a single-layer or double-layer structure of chrome (Cr), molybdenum (Mo) or an aluminum group metal, etc.
Referring to FIG. 3B, the gate insulating film 44 is coated onto the lower substrate 42 provided with the gate metal patterns. Further, semiconductor patterns including the active layer 14 and the ohmic contact layer 48 and source/drain metal patterns including the data line 4, the source electrode 10, the drain electrode 12, the data pad lower electrode 36 and the storage electrode 22 are sequentially formed on the gate insulating film 44 using the second mask process.
More specifically, the gate insulating film 44, an amorphous silicon layer, a n+ amorphous silicon layer and a source/drain metal layer are sequentially provided on the lower substrate 42 provided with the gate patterns by deposition techniques such as the plasma enhanced chemical vapor deposition (PECVD) and the sputtering, etc. Herein, The gate insulating film 44 is made from an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). The source/drain metal is made from molybdenum (Mo), titanium (Ti), tantalum (Ta) or a molybdenum alloy, etc.
Then, a photo-resist pattern is formed on the source/drain metal layer by the photolithography using a second mask. In this case, a diffractive exposure mask having a diffractive exposing part at a channel portion of the thin film transistor is used as a second mask, thereby allowing a photo-resist pattern of the channel portion to have a lower height than other source/drain pattern portion.
Subsequently, the source/drain metal layer is patterned by a wet etching process using the photo-resist pattern to thereby provide the source/drain metal patterns including the data line 4, the source electrode 10, the drain electrode 12 being integral to the source electrode 10 and the storage electrode 22.
Next, the n+ amorphous silicon layer and the amorphous silicon layer are patterned at the same time by a dry etching process using the same photo-resist pattern to thereby provide the ohmic contact layer 48 and the active layer 14. The photo-resist pattern having a relatively low height is removed from the channel portion by the ashing process and thereafter the source/drain metal pattern and the ohmic contact layer 48 of the channel portion are etched by the dry etching process. Thus, the active layer 14 of the channel portion is exposed to disconnect the source electrode 10 from the drain electrode 12.
Then, the photo-resist pattern left on the source/drain pattern is removed by the stripping process.
Referring to FIG. 3C, the protective film 50 including the first and fourth contact holes 16, 24, 30 and 38 are formed on the gate insulating film 44 provided with the source/drain metal patterns using the third mask process.
More specifically, the protective film 50 is entirely provided on the gate insulating film 44 provided with the source/drain metal patterns by a deposition technique such as the plasma enhanced chemical vapor deposition (PECVD). The protective film 50 is patterned by the photolithography and the etching process using the third mask to thereby define the first to fourth contact holes 16, 24, 30 and 38. The first contact hole 16 is formed in such a manner to pass through the protective film 50 and expose the drain electrode 12, whereas the second contact hole 24 is formed in such a manner to pass through the protective film 50 and expose the storage electrode 22. The third contact hole 30 is formed in such a manner to pass through the protective film 50 and the gate insulating film 44 and expose the gate pad lower electrode 28. The fourth contact hole 38 is formed in such a manner to pass through the protective film 50 and expose the data pad lower electrode 36.
The protective film 50 is made from an inorganic material identical to the gate insulating film 44 or an organic material having a small dielectric constant such as an acrylic organic compound, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane), etc.
Referring to FIG. 3D, transparent conductive film patterns including the pixel electrode 18, the gate pad upper electrode 32 and the data pad upper electrode 40 are provided on the protective film 50 using the fourth mask process.
A transparent conductive film is coated onto the protective film 50 by a deposition technique such as the sputtering, etc. Then, the transparent conductive film is patterned by the photolithography and the etching process using a fourth mask to thereby provide the transparent conductive film patterns including the pixel electrode 18, the gate pad upper electrode 32 and the data pad upper electrode 40. The pixel electrode 18 is electrically connected, via the first contact hole 16, to the drain electrode 12 while being electrically connected, via the second contact hole 24, to the storage electrode 22 overlapping with the pre-stage gate line 2. The gate pad upper electrode 32 is electrically connected, via the third contact hole 30, to the gate pad lower electrode 28. The data pad upper electrode 40 is electrically connected, via the fourth contact hole 38, to the data pad lower electrode 36. Herein, the transparent conductive film is formed from indium-tin-oxide (ITO), tin-oxide (TO) or indium-zinc-oxide (IZO).
As described above, the conventional thin film transistor substrate and the manufacturing method thereof adopts a four-round mask process, thereby reducing the number of manufacturing processes in comparison to the five-round mask process and hence reducing a manufacturing cost to that extent. However, since the four-round mask process also still has a complex manufacturing cost and a limit in reducing a cost, there has been required a novel thin film transistor substrate and a novel manufacturing method thereof that is capable of more simplifying the manufacturing process and more reducing the manufacturing cost than the prior art.